1. Field of the Invention
The present invention relates to a circuit under test, a wafer on which a plurality of electronic devices such as semiconductor circuits, etc. are formed, a measuring apparatus and measuring method for measuring an electric characteristic of the wafer, a device manufacturing method for discriminating electronic devices according to unevenness in the electric characteristic of the wafer, and a display apparatus which displays the unevenness in the electric characteristic. Particularly, the present invention relates to a wafer on which a circuit under test such as a TEG (Test Element Group), etc. is formed.
2. Related Art
Recently, semiconductor elements have come to be manufactured with significantly reduced physical dimensions. Along with the dimensional reduction of the elements, the dimensions of defects, which impact the characteristics of the elements, have also been reduced. The dimensional reductions of semiconductor elements and defects have increased unevenness in the characteristics of the elements, which raises a problem in manufacturing a circuit. For example, large unevenness in the threshold voltage, current-voltage characteristic, etc. of MOS transistors gives a great impact on the reliability of the whole circuit and the circuit manufacturing yield.
Further, in addition to such statistical unevenness as described above, local defects such as bit defects, spot defects, etc., which occur at the rate of about a few circuits out of 10,000 to 1,000,000 circuits, are also a factor that influences the reliability and yield of the circuits, raising a problem as well in manufacturing circuits.
As a method for improving the device reliability and manufacturing yield, a possible way is to design a circuit according to the unevenness in the characteristic of elements. That is, by designing a circuit in a manner to tolerate the unevenness, it is possible to improve the device reliability and yield.
Known as a conventional method for measuring unevenness of elements is a method of providing a plurality of TEGs on a wafer on which a plurality of semiconductor circuits are to be formed, and evaluating the characteristic of a plurality of individual elements included in each TEG. That is, the individual elements included in the TEGs are formed through a similar process to that through which elements to be used in actual operation of the circuits are formed, and unevenness in the characteristic of the elements for actual operation are estimated based on the unevenness in the characteristic of the individual elements included in the TEGs.
Presently, no related patent literature has been identified, so indication of any literature is omitted.
However, according to conventional TEGs, a wafer is provided with only a few tens of individual elements to be included in the TEGs, which are through the same process and of the same device size. Hence, measurement of a characteristic cannot be conducted on many elements and unevenness in the characteristic cannot be evaluated accurately. Accordingly, in conventional device designing, it is necessary to build a design having excessive tolerance for unevenness (worst-case design). As a result, the area efficiency of the elements gets worse to cause a problem of increase in the circuit manufacturing costs. Furthermore, such a worst-case design might allow no circuit design using recent semiconductor elements, which are becoming smaller and smaller in size.
What is more, with conventional TEGs, it is impossible to identify the cause of defects which occur locally in the circuits prepared for actual operation. Hence, for identification of defects that occur locally, it is necessary to identify them by evaluating the actual operation circuits which have gone through the whole manufacturing process, requiring a lot of costs and time.